This tutorial will cover topics relating to design in advanced semiconductor technology nodes, especially, 14nm and 10nm.

We will start with a brief introduction on FinFET and highlight PPA scaling from planar devices to FinFET 14nm, 10nm, and 7nm. Then, we will explain key properties of FinFET and its impact on chip design. For example, steep subthreshold slope together with fully depleted channel in FinFET has improved leakage and its variation. This enables aggressive voltage scaling and high Vt cell usage for power reduction. Meanwhile, FinFET has more design constraints (e.g., discretized fins in standard cell design). We will discuss how these constraints can be overcome by innovative technology and design co-optimizations for PPA improvements.

The process technology scale from planar-device-based nodes to FinFET-based nodes was accompanied by a transition in the interconnect patterning to multiple-patterning. For first generation FinFET nodes, that transition started in the local, short-range interconnects for both the “middle-of-line (MOL)” layers and minimum-pitch “back-end-of-line (BEOL)” layers.  Since then, it has proliferated up the BEOL stack. At the same time, the primarily copper-based MOL and lower-level BEOL layers have also hit an inflection point in resistivity (versus line-width), leading to an exponential increase in cost and design complexity needed to overcome the constraints imposed by multiple patterning and the electrical effects imposed by the disproportionate increase in interconnect parasitics. This tutorial will go over the impact of interconnect scaling and design solutions needed to overcome the various constraints and limitations.