Workshop 5: RISC-V Ecosystem - Reshaping the CPU Landscape

1:00 PM–4:00 PM Jun 24, 2018 (America - Los Angeles)

Room 3018


DAC Workshop: RISC-V Ecosystem - Reshaping the CPU Landscape
This session will detail how the free and open RISC-V instruction set architecture (ISA) is creating a paradigm shift in industry, reinvigorating semiconductor design and reshaping traditional business models.

RISC-V ISA and Foundation Overview - Rick O’Connor, RISC-V Foundation
This session will present RISC-V, a free and open ISA. With broad industry adoption, RISC-V is finding its way into applications ranging from IoT to high end servers and supercomputing. This session provides an ISA introduction and a RISC-V Foundation overview.

RISC-V - A Diversity of Core and Accelerator Choices - Markus Levy, NXP
This talk will present some of the notable aspects that make RISC-V attractive: formal support for different instruction subsets, range of OS support (bare metal to hypervisor) and extensibility for custom instructions. The session will review a few of the different RISC-V cores available and provide design considerations of a microcontroller-based core.

RISC-V OS Landscape - Palmer Dabbelt, SiFive
This session will give an overview of the RISC-V operating systems landscape. The session will cover operating systems such as Zephyr and other RTOS offerings that target IoT/microcontroller applications. Attendees will also learn about embedded Linux distributions such as Yocto Linux as well as desktop/server operating systems such as Fedora, Debian, and FreeBSD.

Designing a custom RISC-V core using Chisel - Alex Badicioiu, NXP
In this session, we will show a hands on demo of  the steps required to create custom instruction extensions for RISC-V using available open source tools.