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Timing remains an essential challenge in digital design. To address it, the first paper brings a novel approximate path-based estimation model into a graph-based analysis framework; the second paper considers logic wave optimizations to optimally remove flip-flops while maintaining timing constraints. The third paper seeks to minimize the impact of DVFS sequence on power supply noise by optimizing the transition sequence of clock skipping and clock domain scheduling. Finally, the final paper develops an accurate wirelength distribution model which captures the physical aspects and the design-constraints of the system.
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