Complex power management in today’s SOC low-power ASIC design affects Implementation, Verification, and Signoff aspects. Historically each of these were independent tasks with little inter-dependencies and risks. With the complex low power techniques used by designers, these flows need to work together in delivering a risk free solution with faster turn-around time (TAT).  This session of industry design experts will offer differing opinions on what is needed to achieve a coherent Low Power Solution, and also look into new requirements/strategies to address growing power demands at lower geometries 7nm and below