Interconnects is the backbone of modern chips in the billion-transistor era. This session is composed of four presentations exploring novel features for network-on-chip architectures, spanning, security, efficiency through learning, and features for parallel programming models. The first paper exposes unique security vulnerabilities in emerging photonic interconnects. The second paper opens doors for machine learning techniques to improve the power efficiency of NoCs. The third paper explores hardware support for synchronization primitives for improving the performance of modern multi-core processors. The last paper explores new router architectures for alleviating memory-related bottlenecks in massively parallel accelerators such as GPGPUs.